1. Field of the Invention
The present invention relates to CMOS devices and, more particularly, to a method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor.
2. Description of the Related Art
A complimentary metal oxide semiconductor (CMOS) device is a well-known semiconductor device that includes both n-channel (NMOS) and p-channel (PMOS) transistors. Each transistor has spaced-apart source and drain regions, which are separated by a channel, and a gate that lies over and insulated from the channel.
In order to place more and more transistors on a single die, the physical sizes of the NMOS and PMOS transistors have been continually scaled down, but are beginning to reach the physical scaling limits. The performances of the NMOS and PMOS transistors have steadily improved as the physical sizes of the transistors have been scaled down. However, as the physical sizes of the transistors reach the scaling limit, there is a need for other approaches to improve the performances of the transistors.
One approach to improving the performances of scaled-down transistors is to introduce stress into the channel regions of the NMOS transistors, and strain into the channel regions of the PMOS transistors. Increased channel stress increases the mobility of the electrons in NMOS transistors, while increased channel strain increases the mobility of the holes in PMOS transistors.
One technique for introducing stress into the channel region of an NMOS transistor is known as the stress memorization technique (SMT). In this technique, the NMOS transistor is covered with a stress layer, which is commonly a nitride layer. The stress layer is deposited after an n-type dopant has been implanted into the single-crystal silicon to form source and drain implants, but before the source and drain implants have been annealed to form the source and drain regions. In addition, to save a masking step, the stress layer also commonly covers the PMOS transistors.
Implanting n-type dopants, such as phosphorous or arsenic, into single-crystal silicon damages the lattice. To diffuse the implanted dopant and repair the damage, the doped single-crystal silicon is annealed at a high temperature (e.g., 1100° C.) in a neutral ambient such as N2 to recrystallize the silicon.
This high temperature treatment, however, also increases the stress within the stress layer, which transmits the stress to the channel regions of the NMOS transistors. Thus, when the damaged silicon is recrystallized during the anneal, the recrystallization forms a lattice that supports and maintains the stressed channel region.
As a result, the stress layer can be subsequently removed while still maintaining stressed channel regions for the NMOS transistors. To reduce the stress imparted to the channel regions of the PMOS transistors, a p-type dopant, such as boron, can be implanted and then annealed to form p-type source and drain regions after the n-type implant has been annealed and the stress layer has been removed.
One technique for introducing strain into the channel region of a PMOS transistor is to first etch away portions of the p-type single-crystal-silicon source and drain regions to form source and drain cavities. Following this, silicon germanium (SiGe) is grown in the source and drain cavities to form p-type SiGe source and drain regions. The SiGe source and drain regions have a different lattice spacing than the single-crystal-silicon source and drain regions. The different lattice spacing, in turn, introduces strain to the channel regions of the PMOS transistors.
Although a number of approaches have been utilized to form CMOS devices with a stressed-channel NMOS transistor and a strained-channel PMOS transistor, there is a need for additional approaches which require fewer manufacturing steps and are, therefore, less expensive to fabricate.